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[Software Engineering] 8pic_MCU

Description: 8位MCUIP核的设计与应用（verilog IP核设计）PIC处理器 西安电子科技大学硬件工程师培训资料-Design and Application of 8 MCU IP cores (verilog IP core design) PIC processor Xi an University of Electronic Science and Technology Hardware Engineer training materials
Platform: | Size: 11117568 | Author: 崔琦 | Hits:

[VHDL-FPGA-Verilog] mcu51

Description: 基于IP核的51mcuFPGA程序，有顶层文件图，可以直接运行，有助于对mcu的工作原理和FPGA的理解-IP core based on the 51mcuFPGA program, there are top-level file map, can be directly run, contribute to the working principle of the MCU and FPGA understanding
Platform: | Size: 15726592 | Author: 兰定超 | Hits:

[VHDL-FPGA-Verilog] ReadFifo

Description: QuartusII 15.0版本中，在Qsys中建立的自己定制的符合Avalon总线协议的IP核，实现功能将输入的TS流识别并存储到FIFO中，Nios核再通过总线对数据进行读取-QuartusII 15 version of the Qsys in to establish their own custom Avalon bus protocol in line with the IP core, the realization of the function to enter the TS stream to identify and store the Nios, FIFO kernel and then read the data through the bus
Platform: | Size: 73728 | Author: 艾馨 | Hits:

[Other] uhdsdi

Description: SDI UHD Xilinx IP Core
Platform: | Size: 145408 | Author: hasasoft | Hits:

[VHDL-FPGA-Verilog] LED

Description: 利用QuartusⅡ IPCore实现循环点亮LED.-Use Quartus Ii IP Core for recycling lit LED.
Platform: | Size: 1286144 | Author: xh | Hits:

[VHDL-FPGA-Verilog] AHB2APB_Bridge_example_M7

Description: Cortex-M3+FPGA AHB2APB桥接设计范例, 核心IP不可读，可用。可以综合，测试。-Cortex-M3+ FPGA AHB2APB_Bridge_example， IP core not readable。
Platform: | Size: 215040 | Author: gxliu | Hits:

[VHDL-FPGA-Verilog] fft_core_test

Description: 基于FPGA的FFT的IP核实现，有其详细源码，采用verilog语言编写，内容详细-The FFT based on FPGA IP core implementation, has its source in detail, using verilog language writing, detailed content
Platform: | Size: 8861696 | Author: 赵庆胜 | Hits:

[Software Engineering] SOPCIINIOSII-guiding-book

Description: SOPCIINIOSII实验指导书（第二版）和 实验操作手册，以ALTERA公司的NIOSII IP核为中心，详尽的说明NIOSII的SOPC设计，适用于SOPC-NIOSII EDA/SOPC实验开发平台的系列产品-SOPCIINIOSII experimental guide book (second edition) and the experimental operation manual to ALTERA company NIOSII IP core-centric, detailed description NIOSII of SOPC design for SOPC-NIOSII EDA/SOPC experimental development platform products
Platform: | Size: 8892416 | Author: 淡然 | Hits:

[Program doc] mt46v16m16_256Mb_DDR

Description: DDR控制mt46v16m16芯片的指导性文件-ddr IP core control chip mt46v16m16 guidance document
Platform: | Size: 2419712 | Author: lvhenan | Hits:

[Technology Management] axi_spi_ds742

Description: xilinx，microblaze的spi ip核的datasheet。xilinx官网速度慢，分享给有需要的朋友。 -xilinx, microblaze the spi ip core datasheet. xilinx Officer slow speed of network share to a friend in need.
Platform: | Size: 445440 | Author: sol | Hits:

[Special Effects] myavalonvideo

Description: 自动聚焦视频采集评价计算IP核，TVP5150接口，sobel计算，均值滤波等。可直接添加到SOPC或Qsys中。-Auto focus video capture uation calculation IP core, TVP5150 interface, Sobel calculation, mean filter, etc.. Can be added directly to SOPC or Qsys.
Platform: | Size: 55296 | Author: lpwin81 | Hits:

[VHDL-FPGA-Verilog] pwm

Description: 通过该IP核输出三路pwm波，可用来控制一个舵机和两块L298N驱动板，从而控制电机。-IP core output by the three-way pwm wave can be used to control a servo drive plate and two L298N to control the motor.
Platform: | Size: 2048 | Author: CQ | Hits:

[Other] mina-core-2.0.4.jar

Description: Apache Mina是一个能够帮助用户开发高性能和高伸缩性网络应用程序的框架。它通过Java nio技术基于TCP/IP和UDP/IP协议提供了抽象的、事件驱动的、异步的API。-Apache MINA is a network application framework which helps users develop high performance and high scalability network applications easily. It provides an abstract event-driven asynchronous API over various transports such as TCP/IP and UDP/IP via Java NIO.
Platform: | Size: 569344 | Author: 刘宁超 | Hits:

[VHDL-FPGA-Verilog] spi_ip

Description: SPI总线的IP核，可以实现半双工spi通信-SPI bus IP core, can achieve half-duplex communication spi
Platform: | Size: 1024 | Author: xiewh | Hits:

[VHDL-FPGA-Verilog] DDR3_128M16bit_2Port64bit

Description: Xilinx spartan6 DDR3驱动，编程语言Verilog，基于MCB硬核。-Xilinx spartan6 DDR3 driver based on MCB ip core,coding by verilog.
Platform: | Size: 1553408 | Author: 艾顺义 | Hits:

[VHDL-FPGA-Verilog] PCIe

Description: 使用Altera PCIe IP核,补充PCIe事物层，完成了PCIe设备端硬件设计。Windows和Linux下，安装合适驱动后，可读写PCIe设备。-Use Altera PCIe IP core, supplement PCIe transaction layer, complete PCIe device side hardware design
Platform: | Size: 28978176 | Author: zhaodonglin | Hits:

[Embeded Linux] xilinx_pcie_dma_driver

Description: xilinx官方给的PCI Express DMA IP核的Linux下的驱动代码，以及代码文档-PCI Express DMA IP core of Linux driver code official to under xilinx, and code documentation
Platform: | Size: 551936 | Author: 徐小文 | Hits:

[VHDL-FPGA-Verilog] viterbi_soft

Description: 维特比译码器，调用IP核，软判决输入，开发平台Xilinx Spartan-6系列FPGA-viterbi decoder, using IP core resource, soft decision input,develop platform is Xilinx Spartan-6 series FPGA
Platform: | Size: 3072 | Author: 王沛霖 | Hits:

[VHDL-FPGA-Verilog] 15_IP_core

Description: ata, 3des vgs等ip核。 ECE395 GPU: -ata, 3des vgs and other ip core. ECE395 GPU:
Platform: | Size: 2443264 | Author: Tommy | Hits:

[VHDL-FPGA-Verilog] colorbar

Description: VGA在800*600分辨率屏上显示竖型彩条10份，扫描时钟是通过例化IP核PLL_CLK进行分频得到40MHz-VGA color display type vertical strip 10 parts, scan clock by instantiating the IP core PLL_CLK performed on 800* 600 resolution screen frequency to be 40MHz
Platform: | Size: 1524736 | Author: 文锋 | Hits:
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